Application-Driven System Technology Co-Optimization for 2.5D Edge AI Platforms
Edge AI systems face stringent run-time constraints and tight energy budgets, demanding comprehensive optimization of computing platforms. Nonetheless, existing approaches often focus only on the co-design of hardware and software, but rarely link algorithmic opportunities with system- and technology-level optimizations. Hence, avenues exploiting dynamic machine-learning behaviors on emerging disaggregated System-in-Package platforms remain largely unexplored. To address this challenge, we introduce a cross-level Application-System-Technology Co-Optimization (ASTCO) methodology for dynamic ML encapsulating monolithic and 2.5D chiplet-based architectures. ASTCO explores algorithmic adaptivity, heterogeneous chiplet mapping, and technology scaling within a unified framework. It evaluates integration strategies with or without interposer connectivity and heterogeneous technology nodes, capturing energy-efficiency versus Quality-of-Service (QoS) trade-offs under real-time constraints. We evaluate ASTCO on transformer and CNN models with Early Exits (EEs), representative of dynamic edge ML, performing automated seizure detection. Compared to a monolithic baseline integrating the EE network on a single chip, ASTCO identifies energy-efficient chiplet configurations through cross-level exploration. Results highlight up to 2.2x energy reduction for a 6-layer transformer model, while maintaining real-time guarantees and with very limited QoS impact due to EEs.
A. Burdina, D. Mallasen, A. Levisse, D. Schiavone, G. Ansaloni, and D. Atienza, “Application-Driven System Technology Co-Optimization for 2.5D Edge AI Platforms,” in Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, Evanston IL USA: ACM, Aug. 2026, pp. 1–7. doi: 10.1145/3816440.3818542.@inproceedings{burdina2026ApplicationDriven,
title = {Application-{{Driven System Technology Co-Optimization}} for 2.{{5D Edge AI Platforms}}},
booktitle = {Proceedings of the {{ACM}}/{{IEEE International Symposium}} on {{Low Power Electronics}} and {{Design}}},
author = {Burdina, Anna and Mallasen, David and Levisse, Alexandre and Schiavone, Davide and Ansaloni, Giovanni and Atienza, David},
year = 2026,
month = aug,
pages = {1--7},
publisher = {ACM},
address = {Evanston IL USA},
doi = {10.1145/3816440.3818542},
urldate = {2026-08-17},
isbn = {979-8-4007-2748-1},
langid = {english}
}
