Comparing Different Decodings for Posit Arithmetic

Posit arithmetic has caught the attention of the research community as one of the most promising alternatives to the IEEE 754 standard for floating-point arithmetic. However, the recentness of the posit format makes its hardware less mature and thus more expensive than the floating-point hardware. Most approaches proposed so far decode posit numbers in a similar manner as classical floats. Recently, a novel decoding approach has been proposed, which in contrast with the previous one, considers negative posits to have a negative fraction. In this paper, we present a generic implementation for the latter and offer comparisons of posit addition and multiplication units based on both schemes. ASIC synthesis reveals that this alternative approach enables a faster way to perform operations while reducing the area, power and energy of the functional units. What is more, the proposed posit operators are shown to improve the state-of-the-art of implementations in terms of area, power and energy consumption.

@incollection{murillo2022Comparing,
  title = {Comparing {{Different Decodings}} for {{Posit Arithmetic}}},
  booktitle = {Next {{Generation Arithmetic}}},
  author = {Murillo, Raul and Mallas{\'e}n, David and Del Barrio, Alberto A. and Botella, Guillermo},
  editor = {Gustafson, John and Dimitrov, Vassil},
  year = {2022},
  volume = {13253},
  pages = {84--99},
  publisher = {{Springer International Publishing}},
  address = {{Cham}},
  doi = {10.1007/978-3-031-09779-9_6},
  isbn = {978-3-031-09778-2 978-3-031-09779-9},
  langid = {english}
}